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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
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May 2008
FOD0721, FOD0720, FOD0710 High CMR, 25Mbit/sec Logic Gate Optocoupler
Features
20kV/s minimum CMR 40ns max. propagation delay Data Rate, Non-Return Zero Coding
Description
The FOD0721/0720/0710 family utilizes Fairchild's patented coplanar packaging technology, Optoplanar(R), and optimized IC design to guarantee minimum 20kV/s Common Mode Noise Rejection (CMR) rating. These high-speed logic gate optocouplers consist of a high-speed AlGaAs LED driven by a CMOS IC coupled to a CMOS detector IC, comprising an integrated photodiode, a high-speed transimpedance amplifier and a voltage comparator with an output driver. The CMOS technology coupled to the high efficiency of the LED achieves low power consumption as well as very high speed (40ns propagation delay, 6ns pulse width distortion). These devices are available in a compact 8-pin small outline package.

- 25Mbit/sec (FOD0721 and FOD0720) - 12.5Mbit/sec (FOD0710) Pulse Width Distortion - 6ns (FOD0721) - 8ns (FOD0720 and FOD0710) +5V CMOS compatibility Extended industrial temperate range - -40 to 100C temperature range Safety and regulatory approvals - UL1577, 3750 VACrms for 1 min. (File #E90700, Volume 2) - IEC60747-5-2 pending approval
Applications
Industrial fieldbus communications
- Profibus, DeviceNet, CAN, RS485
Programmable logic control Isolated data acquisition system
Package Dimensions
0.164 (4.16) 0.144 (3.66)
SEATING PLANE
0.202 (5.13) 0.182 (4.63)
0.143 (3.63) 0.123 (3.13)
0.010 (0.25) 0.006 (0.16)
0.021 (0.53) 0.011 (0.28)
0.008 (0.20) 0.003 (0.08) 0.050 (1.27) TYP
0.244 (6.19) 0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX Note: All dimensions are in inches (millimeters)
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7 www.fairchildsemi.com
FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Functional Block Diagram
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VDD1 1 VI 2
8 VDD2 7 NC 6 VO 5 GND2
*
3
GND1 4
*: Pin 3 must be left unconnected Truth Table LED VI H OFF L ON VO H L
Pin Definitions
Pin Number
1 2 3 4 5 6 7 8 GND1 GND2 VO NC VDD2
Pin Name
VDD1 VI Input Supply Voltage Input Data
Pin Function Description
LED Anode - must be left unconnected Input Ground Output Ground Output Data Not Connected Output Supply Voltage
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Absolute Maximum Ratings (TA = 25C unless otherwise specified.)
www..com the absolute maximum ratings may damage the device. The device may not function or be Stresses exceeding
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
TSTG TOPR TSOL VDD1 VI II VDD2 VD IO PD1 PD2
Parameter
Storage Temperature Operating Temperature Lead Solder Temperature Reflow Temperature Profile (Refer to Relow Profile) Input Supply Voltage Input Voltage Input DC Current Output Supply Voltage Output Voltage Average Output Current Input Power Dissipation Output Power Dissipation
Value
-55 to +125 -40 to +100 260 for 10 sec 0 to 6.0 -0.5 to VDD1 + 0.5 -10 to +10 0 to 6.0 -0.5 to VDD2 + 0.5 10 90 70
Units
C C C V V mA V V mA mW mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.
Symbol
TOPR VDD1, VDD2 VIH VIL t r, t f Supply Voltages
Parameter
Ambient Operating Temperature Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Time
Min.
-40 4.5 2.0 0
Max.
+100 5.5 VDD1 0.8 1.0
Unit
C V V V ms
* A 0.1F bypass capacitor must be connected between pins 1 and 4, and 5 and 8 * Pin 3 must be left unconnected
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Electrical Characteristics (TA = -40C to 100C and 4.5V VDD 5.5V, all typicals are at TA = 25C, VDD = 5V)
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Symbol
IDD1L IDD1H IDD1 II IDD2L IDD2H VOH VOH VOL VOL
Parameter
Test Conditions
VI = 0V VI = VDD1
Min.
Typ.
6.5 0.8
Max.
10.0 3.0 13.0 +10
Unit
mA mA mA A mA mA V V
INPUT CHARACTERISTICS Logic Low Input Supply Current Logic High Input Supply Current Input Supply Current Input Current Logic Low Output Supply Current Logic High Output Supply Current Logic High Output Voltage Logic Low Output Voltage VI = 0V VI = VDD1 IO = -20A, VI = VIH IO = -4mA, VI = VIH IO = 20A, VI = VIL IO = 4mA, VI = VIL 4.4 4.0 -10 5.5 5.3 5.0 4.8 0 0.5 0.1 1.0
OUTPUT CHARACTERISTICS 9 9
V V
Isolation Characteristics (TA = -40C to +100C unless otherwise specified.)
Symbol
VISO RISO CISO
Characteristics
Input-Output Isolation Voltage Isolation Resistance Isolation Capacitance VI-O =
Test Conditions
f = 60Hz, t = 1.0 min, II-O 500V(1) 1.0MHz(1) VI-O = 0 , f = 10A(1)(2)
Min.
3750 1011
Typ.* Max.
Unit
VacRMS
0.2
pF
*All typicals at TA = 25C Notes: 1. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together. 2. 3,750 VAC RMS for 1 minute duration is equivalent to 4,500 VAC RMS for 1 second duration.
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Switching Characteristics (TA = -40C to 100C and 4.5V VDD 5.5V, all typicals are at TA = 25C, VDD = 5V)
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Symbol
tPHL tPLH PWD
Parameter
Test Conditions
CL = 15pF CL = 15pF
Min.
Typ.
21 23
Max.
40 40
Unit
ns ns
Propagation Delay Time to Logic Low Output Propagation Delay Time to Logic High Output FOD0710 FOD0720 FOD0721
Pulse Width Distortion, | tPHL - tPLH | PW = 80ns, CL = 15pF PW = 40ns, CL = 15pF PW = 40ns, CL = 15pF 2 2 2 8 8 6 12.5 25 CL = 15pF(3) 5 4.5 VI = VDD1, VO > 0.8 VDD2 VCM = 1000V(4) VI = 0V, VO < 0.8, VCM = 1000V(4) 20 20 40 40 20 ns ns ns Mb/s Mb/s ns ns ns kV/s kV/s
Data Rate tPSK tR tF |CMH| |CML|
FOD0710 FOD0720, FOD0721 Propagation Delay Skew Output Rise Time (10%-90%) Output Fall Time (90%-10%) Common Mode Transient Immunity at Output High Common Mode Transient Immunity at Output Low
Notes: 3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 4. Common mode transient immunity at output high is the maximum tolerable (positive) dVcm/dt on the leading edge of the common mode impulse signal. Vcm, to assure that the output will remain high. Common mode transient immunity at output low is the maximum tolerable (negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to assure that the output will remain low.
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Typical Performance Curves
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Figure 1. Typical Output Voltage vs. Input Voltage
1.9
5
Figure 2. Typical Input Voltage Switching Threshold vs. Input Supply Voltage
VD D2 = 5.0V
- Typical Input Voltage Switching Threshold (V) V
ITH
1.8
4 V - Output Voltage (V)
1.7
3
1.6
2
O
1
1.5
0 0 1 2 3 V I - Input Voltage (V) 4 5
1.4 4.50
4.75
5.00
5.25
5.50
VD D1 - Input Supply Voltage (V)
Figure 3. Typical Propogation Delay vs. Ambient Temperature (FOD0710)
26
Figure 4. Typical Pulse Width Distortion vs. Ambient Temperature (FOD0710)
4
Frequency = 6.25MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V
25
3
PWD - Pulse Width Distortion (ns) 80 100
24
t - Propagation Delay (ns)
2
23
t PLH
1
22
t
PHL
0
21
P
20
-1
19
-2
18 -40
-20
0 20 40 60 TA - Ambient Temperature (C)
-3 -40
-20
0
20
40
60
80
100
TA - Ambient Temperature (C)
Figure 5. Typical Propogation Delay vs. Ambient Temperature (FOD0721/FOD0720)
28 Frequency = 12.5MHz Duty Cycle = 50% V =V = 5.0V
DD1 DD2
Figure 6. Typical Pulse Width Distortion vs. Ambient Temperature (FOD0721/FOD0720)
5
4
Frequency = 12.5MHz Duty Cycle = 50% VD D1 = VDD 2 = 5.0V
26 t P - Propagation Delay (ns) t 24 PWD - Pulse Width Distortion (ns) 60 80 100
3
PLH
2
1
22 tPHL
0
-1
20
-2
18 -40
-3
-20
0
20
40
-40
-20
0
20
40
60
80
100
TA - Ambient Temperature (C)
TA - Ambient Temperature (C)
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Typical Performance Curves (Continued)
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Figure 7. Typical Rise and Fall Time vs. Ambient Temperature
6.00 Frequency = 6.25MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V
Figure 8. Typical Propogation Delay vs. Output Load Capacitance (FOD0710)
28 Frequency = 6.25MHz Duty Cycle = 50% VDD 1 = VDD2 = 5.0V
5.50
27
tr, tf - Rise, Fall Time
5.00 tr
tP - Propagation Delay (ns)
26
25 t
PLH
4.50 tf 4.00
24 tPHL 23
3.50
22
3.00 -40
21
-20 0 20 40 60 TA - Ambient Temperature (C) 80 100
15
20
25 30 35 40 45 CL - Output Load Capacitance (pF)
50
55
Figure 9. Typical Pulse Width Distortion vs. Output Load Capacitance (FOD0710)
1.6 Frequency = 6.25MHz Duty Cycle = 50% V =V = 5.0V
D D1 DD 2
Figure 10. Typical Propogation Delay vs. Output Load Capacitance (FOD0721/FOD0720)
27 Frequency = 12.5MHz Duty Cycle = 50% V DD1 = VD D2 = 5.0V 26
1.4 PWD - Pulse Width Distortion (ns)
t - Propagation Delay (ns)
25 tPLH 24
1.2
1.0
0.8
P
23
tPHL
22
0.6 15 20 25 30 35 40 45 50 55 CL - Output Load Capacitance (pF)
21 15 20 25 30 35 40 45 50 55 CL - Output Load Capacitance (pF)
Figure 11. Typical Pulse Width Distortion vs. Output Load Capacitance (FOD0721/FOD0720)
1.4 Frequency = 12.5MHz Duty Cycle = 50% VDD 1 = VDD 2 = 5.0V
Figure 12. Typical Rise and Fall Time vs. Output Load Capacitance (FOD0710)
12 Frequency = 6.25MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V 10
tf tr, tf - Rise, Fall Time
1.3 PWD - Pulse Width Distortion (ns)
1.2
8
tr
1.1
6
1.0
4 0.9
0.8 15 20 25 30 35 40 45 50 55 CL - Output Load Capacitance (pF)
2 15
20
25 30 35 40 45 CL - Output Load Capacitance (pF)
50
55
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Typical Performance Curves (Continued)
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12 Frequency = 12.5MHz Duty Cycle = 50% VDD1 = VDD2 = 5.0V 10
I DD1 - Input Supply Current (mA)
Figure 13. Typical Rise and Fall Time vs. Output Load Capacitance (FOD0721/FOD0720)
6.5
Figure 14. Typical Input Supply Current vs. Frequency
VDD1 = 5.5V
6.0
5.5
TA = 100C
tr, tf - Rise, Fall Time
tf
8
5.0
TA = 25C
tr
6
4.5
TA = -40C
4.0
4
3.5
2 15
3.0
20 25 30 35 40 45 CL - Output Load Capacitance (pF) 50 55
0
2000
4000 6000 8000 f - Frequency (kHz)
10000
12000
Figure 15. Typical Output Supply Current vs. Frequency
6.0 V DD1 = VD D2 = 5.5V * Pin 6 Floating 5.8
I DD2 - Output Supply Current (mA)
T = 25C
A
5.6 TA = -40C
5.4
T = 100C
A
5.2
5.0 0 2000 4000 6000 8000 f - Frequency (kHz) 10000 12000
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Ordering Information
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Option
R2
Order Entry Identifier
FOD0721 FOD0721R2
Description
Shipped in Tubes (50 units per tube) Tape and Reel (2500 units per reel)
No Suffix
Marking Information
1
721 X YY S1
2
5
3
4
Definitions
1 2 3 4 5 Fairchild logo Device number One digit year code, e.g., `8' Two digit work week ranging from `01' to `53' Assembly package code
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
Carrier Tape Specification
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8.0 0.1 3.5 0.2 0.3 MAX 2 0.05 4.0 0.1 O1.5 MIN 1.75 0.10
5.5 0.05 8.3 0.1 5.2 0.2 12.0 0.3
6.4 0.2 0.1 MAX User Direction of Feed
O1.5 + 0.1/-0
Reflow Profile
300 280 260 240 220 200 180 Temperature (C) 160 140 120 100 80 60 40 20 0 0 60 120 Time (s) 180 270 360 33 Sec 1.822C/Sec Ramp up rate Time above 183C = 90 Sec >245C = 42 Sec 260C
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
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1 0.1F 2 VDD1 = 5V 0V-5V 3 Pulse width = 40ns Duty Cycle = 50% 4 5 6 7 0.1F VO CL VDD2 = 5V 8
tPLH Input VIN
tPHL
5V 50%
Output
90%
VOH
2.5V
VOUT 10% tR tF
VOL
Figure 16. Test Circuit for Propogation Delay Time and Rise Time, Fall Time
1 0.1F SW A VDD1 = 5V B 3 2
8 0.1F VDD2 = 5V VO CL
7
6
4
+ -
5
VCM
1kV GND VOH
Switching Pos. (A) VIN = 5V
VCM
CMH
0.8 x VDD
0.8V VOL
Switching Pos. (B) VIN = 0V
CML
Figure 17. Test Circuit for Instantaneous Common Mode Rejection Voltage
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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FOD0721, FOD0720, FOD0710 -- High CMR, 25Mbit/sec Logic Gate Optocoupler
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TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) EZSWITCHTM * TM
(R)
Fairchild(R) Fairchild Semiconductor(R) FACT Quiet SeriesTM FACT(R) FAST(R) FastvCoreTM FlashWriter(R) *
FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTMe-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM MillerDriveTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R)
(R)
PDP-SPMTM Power220(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM -3 SuperSOTTM -6 SuperSOTTM -8
SupreMOSTM SyncFETTM
(R)
The Power Franchise(R)
TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyPWMTM TinyWireTM SerDesTM UHC(R) Ultra FRFETTM UniFETTM VCXTM
* EZSWITCHTM and FlashWriter(R) are trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that has been discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.
Rev. I33
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
(c)2004 Fairchild Semiconductor Corporation FOD0721, FOD0720, FOD0710 Rev. 1.0.7
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